In recent chip designs a large amount of time and effort are spent designing very low skew clock trees for high performance chips. These clock trees are costly to develop and, because of their high performance nature, they consume a relatively large amount of power. These factors are particularly evident when performing cross-chip data transfers.
Communication across a chip typically involves data paths being buffered if the distance for the communication is beyond the distance that can be communicated in a single cycle of the clock. Latches may also be used in addition to buffers. For example, a combination of buffers and latches is commonly used to account for process, temperature, and voltage variations. Additionally, latched pipelined communication clocks are created with very tight tolerance on the clock skew.
A conventional technique employed to eliminate this tight skew tolerance is to use source synchronous data transfers. In a source synchronous application, a clock signal is sent along with the data from a source (e.g., a remote location on a chip) to a destination (e.g., a local location on the same chip). In such an application, the data is synchronized with the local domain before it can be considered valid for use at the local domain.
Conventional systems and methods for re-synchronizing the data utilize intermediate clocks and latched pipelines. In these methods remote data is sent to an intermediate domain where the clock is shifted to accommodate jitter in the data due to PVT effects. A FIFO, which typically comprises registers, is then needed so that a steady stream of data is provided to the local clock domain. If data was sent from the intermediate domain directly to the local domain without a FIFO, there would be cases where the local clock would capture the same data twice and in some cases may miss blocks of data. However, the use of intermediate clock domains and latched pipelines increases the design complexity and power consumption of a chip.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.